1. Field of the Invention
The present invention relates to a three-phase inverter apparatus using switching devices such as transistors or GTO thyristors. More particularly, the invention relates to improvements in the method of controlling a pulse width modulation (PWM) of the three-level three-phase inverter apparatus, otherwise called an NPC (neutral point clamped) inverter apparatus.
2. Description of the Prior Art
FIG. 1 shows part of a typical prior art three-level inverter that uses GTO's (gate turn-off thyristors) as switching devices. This circuit has a first, a second, a third and a fourth switching device S1, S2, S3 and S4 connected in series between the positive and negative electrodes of a DC power supply having a neutral point output terminal. The junction between the first and the second switching devices and the junction between the third and the fourth switching devices are each connected to the neutral point output terminal via a clamp device such as a diode. The junction between the second and the third switching devices constitutes an inverter output terminal.
Whereas the commonly employed two-level inverter can output only two voltage levels (positive and negative), the circuit outlined above is capable of outputting three voltage levels:
(a) positive potential of the DC power supply when S1 and S2 are turned on;
(b) zero potential of the DC power supply when S2 and S3 are turned on; or
(c) negative potential of the DC power supply when S3 and S4 are turned on.
As a result, the three-phase inverter such as one in FIG. 2 comprising three such single-phase circuits develops less harmonics in its output voltage than the two-level inverter.
A number of methods for controlling the three-level three-phase inverter have been proposed so far. One such method is disclosed in Japanese Patent Application Laid-Open No. HEI/2-261063, "Inverter Apparatus and AC Motor Driving System." FIG. 1 of this disclosure illustrates a PWM pulse processor that performs switching at points of intersection between the carrier and the output voltage command value of each of the phases. The method of the disclosure involves supplying the PWM pulse processor with signals of a zero-phase voltage command processor common to the three phases in order to minimize the voltage fluctuation at the neutral point of the DC power supply.
The PWM system proposed above sets switching times by resorting to the conventional chopping wave comparison; it fails to take into account the effects of the delays in the switching characteristic of the switching devices incorporated, i.e., effects of the minimum on-time (Tonmin) and minimum off-time (Toffmin) constraints. The effects are negligible with such rapid switching devices as transistors. But when it comes to slow-switching GTO thyristors constrained by their prolonged minimum on-time (Tonmin) and minimum off-time (Toffmin) ranging from 50 to 100 microseconds, supplying sine wave output voltage commands only produces severely distorted output waveforms.
The GTO thyristors incorporated will then be damaged if used in conjunction with a PWM circuit disregarding the constraints of Tonmin and Toffmin. The drawback is bypassed by providing an interlock circuit downstream of the PWM circuit that suppresses pulses whose widths are narrower than the minimum on- or off-time (Tonmin or Toffmin). This prevents the switching devices from performing switching of unduly short intervals. Unless such measures were taken, the output current and voltage of the inverter would fail to comply with the commands from a host control system.
A solution to the above difficulty is proposed in a recently published paper, "A Study on PWM Control Methods for Neutral Point Clamped Inverters" (submitted by Miura et al. to the 1991 National Conference on Industrial Applications of the Institute of Electrical Engineers; No. 103, pp. 448-453). The paper discloses a method for avoiding adverse effects of the minimum on-time (Tonmin) constraint when the output voltage command of the inverter is close to zero.
The proposed method is a PWM method based on chopping wave comparison (called unipolar PWM). FIGS. 2, 3 and 6 of the paper are included in this specification as FIGS. 3, 4 and 5, respectively, for reference. As shown in FIG. 3, this PWM method involves using chopping waves X for positive voltage control and chopping waves Y for negative voltage control. The chopping waves X have a positive amplitude ranging from 0 to +Emax, and the chopping waves Y have a negative amplitude of 0 through -Emax. When a control signal eu is positive, the devices S1 and S3 switch at the points of intersection between the signal and the chopping waves X; when the control signal eu is negative, the devices S2 and S4 switch at the points of intersection between the signal and the chopping waves Y.
If the voltage command is lowered as depicted in FIG. 4, issuing commands for soliciting pulses shorter than the minimum on-time (Tonmin) still results in output pulses of the Tonmin duration. That is, the actual output pulses fail to comply with the voltage commands requiring very short pulse widths. According to the proposed method, the above difficulty is circumvented as follows: the command value eu of, say, the U phase is first split in two, eu(+) representing the positive signal part and eu(-) denoting the negative signal part. Thus the command value for the U phase is given as EQU eu=eu(+)+eu(-)
The two signal parts are each modified by a constant value .DELTA.e that is slightly greater than the minimum on-time (Tonmin). That is, the U phase command value is given as EQU eu=(eu(+)+.DELTA.e)+(eu(-)-.DELTA.e)
Arrangements are made so that the devices S1 and S3 switch at the points of intersection between positive chopping waves and the signal eu(+)*=(eu(+)+.DELTA.e). Likewise, the devices S2 and S4 are made to switch at the points of intersection between negative chopping waves and the signal eu(-)*=(eu(-)-.DELTA.e). In this manner, as shown in FIG. 5, the inverter output Vu swings in the positive and negative directions always with a pulse width greater than the minimum on-time (Tonmin). With the minimum on-time-related error thus removed, the voltage of the command value is obtained as an average value.
The methods cited above each concern pulse width control by use of modulated chopping waves. More recent developments are associated with the so-called voltage vector concept. It involves determining the pulse width in accordance with the switching status of each of the phases. One such PWM control method based on the voltage vector concept is disclosed in "DSP Based Space Vector PWM for Three-Level Inverter with DC-Link Voltage Balancing" (Hyo L. Liu, Nam S. Choi and Gyu H. Cho, IECON '91, pp. 197-203). FIG. 7 of this publication is included as FIG. 6 in this specification for reference. In a neutral point voltage control circuit mentioned in the publication, there is brought about a case where the current command vector is an SV vector, as it is called in the publication (the vector corresponds to an intermediate voltage vector a.sub.P, a.sub.N, b.sub.P or b.sub.N, to be described in detail later in this specification). In that case, the time of LSV (corresponding to vector a.sub.N or b.sub.N) is arranged to be increased and the time of USV (corresponding to vector a.sub.P or b.sub.P) shortened if the deviation of the neutral point voltage is positive.
A special synchronization modulating method is devised whereby the USV and LSV are used on balance. It this manner, as the authors contend, the neutral point is balanced and, in the triangular regions .DELTA.1, .DELTA.2, .DELTA.3 and .DELTA.4 of FIG. 6, the voltage vectors are output in the following order (.DELTA.4 is in fact not noted because it is in symmetry with .DELTA.3):
.DELTA.i: 0N0--P00--000 PA1 .DELTA.2: 0N0--PN0--P00 PA1 .DELTA.3: 0N0--P0N (typographic error; PN0 is correct) --PNP
This modulation method, as depicted in FIG. 6, is characterized in not using the intermediate voltage vector of either the positive or the negative side at intervals of 60 degrees. Of the three zero vector variations, only 000 is used; PPP and NNN are not utilized.
Prior art three-level three-phase inverter apparatuses are typically controlled as outlined above. In the representative PWM control setup whereby the switching time is controlled by use of modified chopping waves, the voltage command value of sine waves is first compared with the modified chopping waves. The logical output from the comparison is used to control the signal for driving the switching devices of each of the phases. The constraints involved with this setup are not conducive to pursuing optimum control systems that comply with the circuit conditions specific to the three-level inverter.
Under the cited control method utilizing the voltage vector concept, there exist a plurality of voltage vectors which are different in switching status between phases but which have the same vector quantity each. Of these voltage vectors, only one is selected and, based on that vector alone, each triangular region is specified. It follows that an optimum control system cannot be pursued for each of the different regions. Consequently it is difficult to achieve favorable control characteristics as a whole.